1. Field of the Invention
The present invention relates to a technology for an SRAM circuit as a semiconductor memory device, and more particularly to a technology for screening bits which are defective in cell characteristics including static noise margin, write level or the like, which is caused by over-time deterioration or operation noise of a logic circuit located in the vicinity of the SRAM.
2. Description of the Background Art
In recent precision semiconductor devices, increase in random variance in transistor (hereinafter, referred to as “Tr”) characteristics caused by size reduction, and variance in SRAM characteristics caused by the random variance in Tr characteristics, are serious problems. In semiconductor devices of the conventional generation, it was sufficient to obtain a certain degree of beta ratio, which is the ratio of the driving capability of a drive Tr with respect to the driving capability of an access Tr. The cell size was substantially determined in consideration of only the processing conditions during the production. Therefore, the influence of the random variance was trivial enough to be buried in the discussion on the inter-lot variance (hereinafter, referred to the “global variance”).
However, in semiconductor devices of the 65 nm rule or newer process generations, the ratio of random variance in each chip with respect to global variance has been rapidly increasing due to the size reduction. Therefore, with the conventional structure, it is very difficult to produce devices having good cell characteristics in the Mbit order. In order to solve this, techniques are being studied by which, for example, good cell characteristics are obtained by making the gate length, gate width or other elements of the device size larger than the processing limit, or requirements for the SRAM cell characteristics are alleviated by dynamically controlling the power supply potential from the peripheral circuits to the memory cells. See, for example, “ISSCC2005 Low-Power Embedded SRAM Modules with Expanded Margins for Writing”, Hitach, Renesas.
Despite such efforts, it is becoming more difficult to obtain good products than in the past process generations. Cell characteristic margins are being reduced with certainty. Important SRAM characteristics include static noise margin (hereinafter, referred to as “SNM”) which indicates the cell stability during the read operation, write level indicating the ease of writing, cell current during the read operation, and standby current. With reference to FIG. 18, a mechanism by which an insufficient SNM leads to malfunction will be described.
It is assumed now that bit lines 1001 and 1002 are precharged to a High potential, an intermediate node 1003 is at a Low potential, an intermediate node 1004 is at a High potential, and the lines 1001 and 1002 and the nodes 1003 and 1004 are all stable. A read operation is performed from this state. When the potential of a word line 1000 becomes High, an access Tr 1005 is place into an ON state. Since the access Tr 1005 and a drive Tr 1012 in an ON state each other, the potential of the intermediate node 1003 becomes slightly higher than the Low potential. If the potential of the intermediate node 1003 exceeds the logic threshold of an inverter 1007, the inverter 1007 performs inversion. As a result, the intermediate node 1004 is driven from a High potential to a Low potential. This causes malfunction. The logic threshold of the inverter 1007 becomes high when a load Tr 1009 has a high capability and a drive Tr 1010 has a low capability. Namely, when the load Tr 1009 has a lower Vt potential, there is a larger margin for the rise of the potential of the intermediate node 1003. The SNM is deteriorated when the access Tr 1005 is at a Low Vt potential, the drive Tr 1012 is at a High Vt potential, the load Tr 1009 is at a High Vt potential, and the drive Tr 1010 is at a Low Vt potential. The problem of variance also occurs regarding other characteristics including write level and cell current.
Under the circumstances, the present inventors found the practical causes of the above problems.
First, the cell characteristics are deteriorated over-time at a high possibility. This was not conspicuous in the devices in the conventional process generations because there was a large margin for the cell characteristics. However, this is conspicuous today because the margin for good cell characteristics is very small, or slightly defective bits are handled by the redundancy rescue technology and shipped as satisfactory products. In addition, SNM is sensitive against the power supply noise or the like as is clear from the name. Therefore, some memories operate normally when independently inspected, but become defective due to the noise supplied to the power supply system as a result of the operation of a great number of logics in the vicinity thereof.
Specific examples of the over-time deterioration include NBTI (Negative Bias Temperature Instability) deterioration of Pch Tr. This is a phenomenon of device deterioration that when the state where a Pch Tr is in an ON state, i.e., the state where the gate is at a low potential, is continued, the Vt potential of the Pch Tr is shifted to a higher potential. Examples of the over-time deterioration of Nch Tr include hot carrier deterioration discussed regarding the 5V-and 3V-system generations.
In the low-voltage precision process, the power supply itself is lower and the NBTI deterioration of Pch Tr occurs by merely placing the Pch Tr into a standby state with the power supply being ON. By contrast, the hot carrier deterioration of Nch Tr occurs only during a transition operation in which the LSI is operated and the gate is in an intermediate potential state. For this and other reasons, the hot carrier deterioration of Nch Tr is not considered as a serious problem.
Due to the difference in the over-time deterioration mode between Pch Tr and Nch Tr or the like, it may occur that the Vt potential of the Nch Tr is kept almost the same and the Vt potential of only the Pch Tr is raised from the initial state. In the state where there is almost no margin between the operation limit and the global variance assumed from the point of device production, when the Pch load Tr is deteriorated over-time and the Vt potential thereof is raised, an SRAM which had a good SNM at the pre-shipment test exhibits SNM deterioration due to the reduction in the logic threshold of the inverter with which the SRAM is to be incorporated.
The NBTI deterioration influences the write level corresponding to the write margin in addition to the SNM corresponding to the read margin. It is true that as the Vt potential of the Pch Tr is raised, the write is made easier. However, the stress by the NBTI deterioration varies in accordance with the potential state. Therefore, among complementary inverter latches, the NBTI deterioration may occur only in the Pch which is in an ON state for an extended period of time. As a result, whereas the Vt potential of one load Tr 1009 is not shifted, the Vt potential of the other load Vt 1011 may raised over-time due to NBTI deterioration. When the potential of the bit line 1002 is lowered to perform a write operation, the potential of the intermediate node 1004 becomes Low since the load Tr 1009 and an access Tr 1006 in an ON state each other. The inverter 1008 receives this potential. When the Vt potential of the load Tr 1011 is high, the logic threshold of the inverter 1008 is low, and the write level may be deteriorated so that the write operation cannot be performed unless the potential of the intermediate node 1004 is further lowered. In the above, the deterioration on the Pch Tr side is described, but the deterioration on the Nch Tr side may possibly become conspicuous in the future. The over-time deterioration in the cell characteristics is not limited to the situations described above.
Defects may occur due to an operational environment in addition to the over-time deterioration. For example, even when no problem is found by an independent SRAM macro test or evaluation using a tester, defects may occur by the highly active operation performed by the logic section located in the vicinity of the SRAM on the LSI or by the low strength of the board on which the SRAM is mounted. The present inventors concluded that it is necessary to obtain an appropriate cell characteristic margin against the cell characteristic deterioration caused over-time or by an operational environment.